From 383b4cb0fc05bef07fa33c2549fc6962ff6a2324 Mon Sep 17 00:00:00 2001 From: Tobias Brunner Date: Fri, 3 Jul 2026 08:06:20 +0200 Subject: [PATCH] aesni: Make sure the CPU supports SSSE3 There are no real CPUs that support AES-NI/PCLMULQDQ but don't support SSSE3. However, in VMs the vCPU features might not exactly match those of the underlying CPU. So if SSSE3 is missing, the PSHUFB instruction would cause a SIGILL. The referenced commit is the first one that uses the `_mm_shuffle_epi8` intrinsic. Fixes: 74d43cbde999 ("aesni: Implement a AES-NI based CTR crypter using the key schedule") --- src/libstrongswan/plugins/aesni/aesni_plugin.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/src/libstrongswan/plugins/aesni/aesni_plugin.c b/src/libstrongswan/plugins/aesni/aesni_plugin.c index 77e715b86..55e5b1d93 100644 --- a/src/libstrongswan/plugins/aesni/aesni_plugin.c +++ b/src/libstrongswan/plugins/aesni/aesni_plugin.c @@ -96,7 +96,8 @@ METHOD(plugin_t, get_features, int, }; *features = f; - if (cpu_feature_available(CPU_FEATURE_AESNI | CPU_FEATURE_PCLMULQDQ)) + if (cpu_feature_available(CPU_FEATURE_AESNI | CPU_FEATURE_PCLMULQDQ | + CPU_FEATURE_SSSE3)) { return countof(f); }